1. Field of the Invention
The invention relates in general to a method of improving memory performance, and more particularly to a method of improving flash memory performance.
2. Description of the Related Art
The operation of EEPROM non-volatile memory devices, such as FLOTOX (floating gate tunnel oxide) flash memory developed by Intel, relies on the charge stored in a floating gate to induce changes in the threshold voltage. FIG. 1A illustrates cross sectional view of a relevant portion of an archetypal flash memory cell. The memory cell 100 consists of a substrate 110, a thin gate dielectric layer 120 (hereinafter “tunnel oxide”) formed on the surface of the substrate 110, and a gate structure 130 overlying the tunnel oxide 120. A gate insulating layer 140 is deposited to enclose the gate structure 130, and then chemically etched to form sidewall spacers 140a and 140b as shown in FIG. 1B.
FIG. 2A illustrates the composition of the gate structure 130. The gate structure 130 includes a first polysilicon layer acting as a floating gate 136 overlying the tunnel oxide 120 and an interpoly dielectric layer 134 overlying the floating gate 136. The interpoly dielectric layer 134 is often a multi-layer insulator, such as an oxide-nitride-oxide (ONO) layer having two oxide layers 134-1 and 134-3 and a nitride layer 134-2. Additionally, a second polysilicon layer that acts as a control gate 132 overlies the interpoly dielectric layer 134 to complete the gate structure 130.
Since the charges are stored in the floating gate, the sidewall quality of gate structure dominates in the retention of flash memories. Usually a cell reoxidation process is performed after the gate structure formation to recover the damages induced by etching process. On the other hand, as the size of memory cells become smaller, it becomes advantageous to apply lower bias voltages on the control gate 132 for programming the memory cell 100. Lower voltages can be achieved by reducing the thickness of the interpoly dielectric layer 134, thereby increasing the control gate coupling ratio (GCR), which is defined as the voltage ratio of the control gate coupling to the floating gate. However, during the cell reoxidation of the gate structure 130, serious encroachment issues arising from conventional cell reoxidation process increases the thickness of the interpoly dielectric layer 134 so as to reduce GCR.
That is, in some conventional processes, the gate structure is first thermally treated by reoxidation before being deposited a gate insulating layer thereon to form sidewall spacers. However, such process is likely to suffer encroachment, in which oxygen is found diffusing into the tunnel oxide and the interpoly dielectric layer. Such encroachments significantly affect the performance of the memory cell. An approach to reduce encroachment issue is to utilize in-situ steam generation (ISSG) process, such as one disclosed in U.S. Pat. No. 6,624,023, assigned to the assignee of this invention. Another approach to overcome such problems is to deposit a gate insulating layer and perform reoxidation on the gate insulating layer enclosed gate structure 130 of FIG. 1A, such as by diffusion oxidation using a furnace, before the gate insulating layer is chemically etched to form sidewall spacers 140a and 140b. With the added gate insulating layer, the goal of such approach is to try slowing down the rate of reaction, thus decreasing encroachment.
However, as shown in FIG. 2B, the above mentioned methods are still found in the gate structure 130 to have considerable encroachment 138-1 and 138-2 occurring between the interface of interpoly dielectric layer 134 and polysilicon layer 132, and the interface of interpoly dielectric layer 134 and polysilicon layer 136. The introduced oxygen O2 is also found encroaching into the tunnel oxide 120, as shown by 150(1) and 150(2) in the relevant portion of a memory cell 300 of FIG. 3. The O2 encroachments 138-1 and 138-2 inevitably increase the thickness of the interpoly dielectric layer 134. Since a thicker interpoly dielectric layer equates to a smaller equivalent capacitance, and GCR is proportional to the capacitance of the ONO layer (interpoly dielectric layer), GCR inevitably decreases, which in turn reduces memory cell operation speed. The encroachment in the tunnel oxide 120 also decreases the drain coupling ratio (DCR) and the source coupling ratio (SCR), which also acts to reduce the memory cell operation. Hence, the required programming voltage applied on the control gate 132 needs to be undesirably increased in order to prevent slowing down of memory cell operation.
Accordingly, there is a need to provide a method of improving flash memory performance by reducing encroachment issues in the interpoly dielectric layer and the tunnel oxide.